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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-28221-1E
ASSP For Video Applications
CMOS
3 ch 8-bit 162 MSPS A/D Converter
MB40C338V
s DESCRIPTION
MB40C338V is a high-speed 3 ch A/D converter using a fast CMOS technology.
s FEATURES
* * * * * * * * * * * * Resolution No. of A/D channels Linearity error Maximum conversion rate Power supply voltage Digital input voltage range Digital output voltage range Video amp. input voltage range Video amp. gain A/D input capacity Power dissipation Additional features : 8 bit : 3 ch : 0.40 %(typical) : 162 MSPS (minimum) : 3.3 V (typical : internal circuit) : TTL level : 3.3 V CMOS level : 0.7 VP-P (typical) : 1.9 double fixed : 15 pF (typical) : 1100 mW (typical) : PLL circuit Video amp. circuit (1.9 double fixed gain, OFF operation is possible) CLAMP circuit VRT AMP circuit (RGB 3 ch separate) VRB AMP circuit (RGB 3 ch common) Overflow output High impedance output, power down function : LQFP120 (16 mm x 16 mm, lead pitch : 0.5 mm) 120-pin plastic LQFP
* Package
s PACKAGE
(FPT-120P-M21)
MB40C338V
s PIN ASSIGNMENT
(TOP VIEW)
PVSS PVDD HSYNC HHOLD PVDD LPF PVSS RREF RVRT GVRT BVRT RVM AVSS AVDD DVDD DVSS OF DSYNC DSYNCB COUT EXPCLK EXPCLKB EXCLK ADCLKA ADCLKB CLK CLKB DVDD DVSS AVSS RVIN VRB GVIN GVM BVIN BVM VREF PCLP AVDD AVSS RADIN VRBM GADIN VESD BADIN RVRTM GVRTM BVRTM RVCLP GVCLP BVCLP AVSS AVDD CS CK DATA DVSS DVDD (MSB) BDB7 BDB6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RDA0 (LSB) RDA1 RDA2 RDA3 RDA4 RDA5 RDA6 RDA7 (MSB) DVDD DVSS AVSS AVDD RDB0 (LSB) RDB1 RDB2 RDB3 RDB4 RDB5 RDB6 RDB7 (MSB) DVDD DVSS GDA0 (LSB) GDA1 GDA2 GDA3 GDA4 GDA5 GDA6 GDA7 (MSB)
2
BDB5 BDB4 BDB3 BDB2 BDB1 (LSB) BDB0 DVSS DVDD (MSB) BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 (LSB) BDA0 AVDD AVSS DVSS DVDD (MSB) GDB7 GDB6 GDB5 GDB4 GDB3 GDB2 GDB1 (LSB) GDB0 DVDD DVSS
(FPT-120P-M21)
MB40C338V
s PIN DESCRIPTION
Pin No. 9, 23, 47, 79, 107 28, 38, 50, 59, 70, 82, 93, 106 116, 119 14 10, 22, 48, 80, 91, 108 27, 37, 49, 60, 69, 81, 92, 105 114, 120 1 3 5 11 13 15 19 20 21 16 17 18 112 111 110 12 2 109 4 6 25 26 24 Symbol AVDD Analog power supply (+3.3 V) Description
DVDD PVDD VESD AVSS
Digital power supply (+3.3 V) PLL Power supply pin (+3.3 V) Digital input power supply for protect device (+3.3 V or +5 V) Analog power supply ground pin (0 V)
DVSS PVSS RVIN GVIN BVIN RADIN GADIN BADIN RVCLP GVCLP BVCLP RVRTM GVRTM BVRTM RVRT GVRT BVRT VRBM VRB RVM GVM BVM CK DATA CS
Digital power supply ground pin (0 V) PLL Power supply ground pin (0 V) 1.9 double amp. input pin
A/D converter input pin This pin inputs directly is possible when 1.9 double amp.OFF
Clamp voltage setting input pin
Reference voltage output pin on top side
Reference voltage input pin on top side Reference voltage output pin on bottom side Reference voltage input pin on bottom side Reference 1/2 voltage output pin (Add 0.1 F for AVSS) Serial data transfer clock input pin Serial data input pin Chip select signal input pin It is possible to input to the shift register at CS falling The content of the shift register is executed at CS rising. Clock input pin for A/D converter (CMOS level) Fix to "L" level when unused.
98
EXCLK
Note: The values in parentheses are standard.
(Continued)
3
MB40C338V
(Continued)
Parameter 99 100 8 113 103 102 95 94 97 96 83 to 90 61 to 68 39 to 46 71 to 78 51 to 58 29 to 36 101 115 117 118 7 104 Symbol EXPCLKB EXPCLK PCLP RREF DSYNC DSYNCB CLK CLKB ADCLKA ADCLKB RDA7 to RDA0 GDA7 to GDA0 BDA7 to BDA0 RDB7 to RDB0 GDB7 to GDB0 BDB7 to BDB0 COUT LPF HHOLD HSYNC VREF OF Digital output pin (Port A) RDA7, GDA7, BDA7 : MSB RDA0, GDA0, BDA0 : LSB Digital output pin (Port B) RDB7, GDB7, BDB7 : MSB RDB0, GDB0, BDB0 : LSB PLL counter output pin External capacitor/resistor connection pin Phase detector operation is hold by input "H" level Horizontal sync signal input pin Internal voltage output pin (Add 3.3F for AVSS) Overflow output pin ("H" level output at overflow) Clock output pin (See " s TIMING DIAGRAM ".) Description Differential clock (negative-phase) input pin for A/D converter Fix to "H" level when unused. Differential clock (positive-phase) input pin for A/D converter Fix to "L" level when unused. Clamp pulse input pin Internal current setting pin (Add 12 k for AVSS) Delay sync signal output pin Inverted delay sync signal output pin
PECL level
Note: The values in parentheses are standard.
4
MB40C338V
s BLOCK DIAGRAM
VESD
AVDD
DVDD
RVRT RVRTM VRB VRBM
RVM GVM BVM
PCLP
OF
RADIN
x 1.9
AMP + CLAMP + A/D A ch 8 8 bit A/D Buffer 8
x 3 ch
RVIN
RDA0 RDA7
B ch 8 8 bit A/D Buffer 8 RDB0 RDB7
RVCLP
Buffer
ADCLKA ADCLKB AVSS DVSS
PLL block
RESET 2 bit (0 3 CLK) CLK Delay Delay 1/2
Buffer
Buffer Buffer
DSYNC DSYNCB
6 bit (32 divide, 2CLK)
HSYNC POL (1 bit) PD CP VCO MUX DIV 2 bit (1 1/8)
Buffer Buffer
CLK CLKB
Counter HHOLD (12 bit) COUT LPF Filter EXPCLKB EXCLK EXPCLK
11 bit Shift Reg
PVSS PVDD CK DATA CS
5
MB40C338V
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Symbol AVDD, DVDD, PVDD VESD RVIN, GVIN, BVIN, RADIN, GADIN, BADIN, RVCLP, GVCLP, BVCLP, RVRT, GVRT, BVRT, RVRTM, GVRTM, BVRTM, VRB, VRBM, RVM, GVM, BVM, VREF, RREF RDA0 to RDA7, RDB0 to RDB7, GDA0 to GDA7, GDB0 to GDB7, BDA0 to BDA7, BDB0 to BDB7, DSYNC, DSYNCB, OF, COUT, CLK, CLKB, ADCLKA, ADCLKB LPF CK, DATA, CS, EXPCLKB, EXPCLK, PCLP, EXCLK, HHOLD, HSYNC Storage temperature *1 : Do not exceed +4.0 V. *2 : Do not exceed +7.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. TSTG Rating Min. -0.3 -0.3 Max. +4.0 +7.0 Unit V V
-0.3
AVDD+0.3*1
V
Input/output voltage
-0.3
DVDD+0.3*1
V
-0.3 -0.3 -55
PVDD+0.3*1
V
VESD+0.3*2 +125
V C
6
MB40C338V
s RECOMMENDED OPERATING CONDITIONS
Parameter Symbol AVDD, DVDD Power supply voltage A/D converter input voltage Analog reference voltage: T Analog reference voltage : B Analog reference voltage range Video AMP input voltage Clamp input voltage Digital "H" level input voltage Digital "L" level input voltage Digital "H" level output current Digital "L" level output current PLL counter HSYNC input frequency range HHOLD set up time HHOLD hold time Clamp pulse width CK clock pulse width DATA set up time DATA hold time CS set up time CS hold time CS "H" level hold time Operating temperature range PVDD VESD VADIN VRT VRB VRT - VRB VIN (P-P) VCLP VIHD VILD IOHD IOLD PC fHSYNC tsHHOLD thHHOLD tWCLP tWCKL, tWCKH tsDATA thDATA tsCS thCS tWCSH Ta Value Min. 3.00 3.00 3.00 VRB 0.6 1.0 0.5 0.6 2.5 0 -400 100 10 20 20 0.5 100 30 30 50 50 100 -20 Typ. 3.30 3.30 2.2 0.7 1.5 VRB Max. 3.60 3.60 5.25 VRT AVDD - 0.6 1.8 0.9 1.7 VESD 0.5 1.6 4095 100 70 Unit V V V V V V V VP-P V V V A mA kHz ns ns s ns ns ns ns ns ns C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
7
MB40C338V
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics in Analog Section
* Power supply current (AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, Ta = -20 C to +70 C) Value Parameter Symbol Unit Min. Typ. Max. AIDD DIDD PIDD ISB 220 100 16 10 310 110 20 mA mA mA mA
Analog power supply current Digital power supply current Power supply current PLL section (@ fVCOH = 162 MHz, Icp = 0.5 mA, DIV = 1/1) Standby current * A/D Block Parameter Resolution Linearity error (DC Accuracy) Differential linearity error (DC Accuracy) Analog reference voltage input current ADIN input capacity * Video AMP Block Parameter Video AMP gain Video AMP output voltage range Video AMP frequency width Video AMP input capacity * CLAMP Block Parameter VCLP input current Clamp voltage * PLL Block
(AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, Ta = -20 C to +70 C) Value Symbol Unit Min. Typ. Max. LE DLE IRT, IRB CADIN -0.8 -0.36 8 0.4 0.2 5 15 +0.8 +0.65 20 bit % % A pF
(AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, Ta = -20 C to +70 C) Value Symbol Unit Min. Typ. Max. GAMP VAMPOUT BW CVIN 1.8 0.5 1.9 250 5 2.0 AVDD - 0.6 V MHz pF
(AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, Ta = -20 C to +70 C) Value Symbol Unit Min. Typ. Max. ICLP VCLAMP VCLP - 0.1 5 VCLP 20 VCLP + 0.1 A V
(AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, Ta = -20 C to +70 C) Value Parameter Symbol Unit Min. Typ. Max. Ptj 1.0 1.5 ns
CLK jitter (@ fHSYNC = 79.98 kHz, fCLK = 135.0 MHz)
8
MB40C338V
2. DC characteristics in Digital Section
(AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, Ta = -20 C to +70 C) Parameter Digital input current Digital "H" level output voltage Digital "L" level output voltage Symbol IID VOHD VOLD Value Min. -20 DVDD - 0.4 Typ. Max. 5 0.4 Unit A V V
3. Switching Characteristics
(AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, Ta = -20 C to +70 C) Parameter A/D Maximum conversion rate Aperture time VCO oscillation frequency CLK output delay time Timing diagram 1 Digital output delay time Timing diagram 2 DSYNC output delay time VCOL VCOH Timing diagram 1 Timing diagram 2 Symbol fS1 fS2 tAD fVCOL fVCOH tpd (HSYNC-CLK) tpd (CLK-ADCLK1) tpd (CLK-DATA1) tpd (CLK-ADCLK2) tpd (CLK-DATA2) tpd (CLK-DSYNC) Value Min. 100 162 75 85 1.0 0.0 2.5 0.0 2.5 0.5 Typ. 1.5 2.0 1.0 4.0 1.0 4.0 1.5 Max. 140 162 4.0 2.0 6.0 2.0 6.0 2.0 Unit MSPS MSPS ns MHz MHz ns ns ns ns ns ns
s DIGITAL OUTPUT BUFFER LOAD CIRCUIT
To the measurement point Measurement point
CL = 15 pF
DVSS
Note: CL includes a stray capacitance of a probe and a fixture.
9
MB40C338V
s SERIAL DATA SETTING (MSB FAST)
(Address) LSB RES D0 0 0 0 0 1 2 1 0 1 3 1 1 0 0 0 4 0 0 0 0 1 1 5 1 1 1 1 D1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 D2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 X X X 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D8 X X X 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Data) MSB D9 D10 X X X 1 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function CE : 0 = operation mode, 1 = all function power off DSEL : 0 = demultiplex output, 1 = straight output Video AMP : 0 = operation , 1 = off Counter low ranking 8 bit Counter high ranking 4 bit CLK delay adjust*1 : td = N / (32 x fCLK) HSYNC polarity : 0 = through, 1 = inversion A/D converter output : 0 = operation, 1 = high impedance CLK output : 0 = on, 1 = "L" CLKB output : 0 = on, 1 = "L" DSYNC output : 0 = on, 1 = "L" DSYNCB output : 0 = on, 1 = "L" ADCLKA output : 0 = on, 1 = "L" ADCLKB output : 0 = on, 1 = "L" DSYNC delay*2 : 0, 1, 2, 3 CLK change : 0 = VCO, 1 = External clock External clock input : 0 = CMOS, 1 = PECL Counter operation : 0 = on, 1 = off Charge pump current*3 : 0.1 mA, 0.5 mA, 1 mA VCO select : 0 = VCOL, 1 = VCOH Divider setting*4 : 1, 1/2, 1/4, 1/8
*1 : Setting at 6bit Resolution : 1/32 x CLK, Setting range : 0 to 63/32 x CLK *2, *3, *4 : See under table Setting DSYNC delay*2 Charge pump current* Divider setting*
4 3
0 (0, 0) 0 CLK 0.1 mA 1/1
1 (1, 0) 1 CLK 0.5 mA 1/2
2 (0, 1) 2 CLK 1.0 mA 1/4
3 (1, 1) 3 CLK 1/8
10
MB40C338V
Example: input at 16 bit
MSB LSB DATA Address
DATA input
Invalid data
(5 bit)
(8 bit)
(3 bit)
CS input
s RECOMMENDED VALUE OF SERIAL DATA SETTING
fCLK (MHz) UXGA SXGA 162.000 157.500 135.000 108.000 94.500 XGA 78.750 75.000 65.000 56.250 SVGA 50.000 49.500 40.000 36.000 VGA 31.500 25.175 25.149 29.375 PAL 22.031 14.688 24.545 NTSC 18.409 12.273 fHSYNC (kHz) 75.000 91.146 81.130 64.904 68.677 60.023 56.476 48.363 53.674 48.077 46.875 37.879 43.269 37.861 31.469 31.436 15.625 15.625 15.625 15.734 15.734 15.734 Counter 2160 1728 1664 1664 1376 1312 1328 1344 1048 1040 1056 1056 832 832 800 800 1880 1410 940 1560 1170 780 Icp (mA) 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 VCO select VCOH VCOH VCOH or VCOL VCOH or VCOL VCOH or VCOL VCOL VCOH VCOH or VCOL VCOH or VCOL VCOH or VCOL VCOH or VCOL VCOL VCOH VCOH or VCOL VCOH or VCOL VCOH or VCOL VCOH or VCOL VCOH or VCOL VCOH or VCOL VCOH or VCOL VCOH VCOH or VCOL Divider 1/1 1/1 1/1 1/1 1/1 1/1 1/2 1/2 1/2 1/2 1/2 1/2 1/4 1/4 1/4 1/4 1/4 1/4 1/8 1/4 1/8 1/8 fVCO (MHz) 162.000 157.500 135.000 108.000 94.500 78.750 150.000 130.000 112.500 100.000 99.000 80.000 144.000 126.000 100.700 100.596 117.500 88.125 117.500 98.180 147.270 98.180
VCO select : VCOH (fVCO = 85 MHz to 162 MHz) VCOL (fVCO = 75 MHz to 140 MHz) fCLK = fHSYNC x Counter fVCO = fHSYNC x Counter/Divider 11
MB40C338V
s TIMING DIAGRAM
* Straight Output Mode (Timing Diagram 1)
VIHD HSYNC input VILD
tpd (HSYNC-CLK)
VOHD CLK output CLKB output VOLD
tpd (CLK-DSYNC) VOHD VOLD tpd (CLK-ADCLK1)
DSYNC output
VOHD ADCLKA output VOLD VOHD ADCLKB output VOLD
N N+1 tAD N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9
ADIN input
tpd (CLK-DATA1) VOHD
DA0 to DA7 output
VOLD VOHD
X
X
X
X
X
X
X
X
N
N+1
N+2
N+3
DB0 to DB7 output
VOLD
ALL "L" fix
VOHD OF output VOLD
X
X
X
X
X
X
X
X
N
N+1
N+2
N+3
* ADIN input - Sampling at CLK rising (at CLKB falling) * DA0 to DA7 - Output (after 5 CLK + tpd (CLK-DATA1) from sampling ) at CLK rising (at CLKB falling)
12
MB40C338V
* Demultiplex Output (in- phase) Mode (Timing Diagram 2)
VIHD HSYNC input VILD
tpd (HSYNC-CLK)
VOHD CLKB output CLK output VOLD
tpd (CLK-DSYNC)
VOHD DSYNC output VOLD
tpd (CLK-ADCLK2)
VOHD ADCLKA output VOLD VOHD ADCLKB output VOLD
N N+1 tAD N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9
ADIN input
tpd (CLK-DATA2)
VOHD DA0 to DA7 output VOLD VOHD DB0 to DB7 output VOLD VOHD OF output VOLD
X
X
X
X
X
N
N+2
X
X
X
X
X
N+1
N+3
X
X
X
X
X
N
N+2
* ADIN input - Sampling at CLK rising (at CLKB falling) * DA0 to DA7 - Output (after 6 CLK + tpd (CLK-DATA2) from sampling ) at CLK rising (at CLKB falling) * DB0 to DB7 - Output (after 5 CLK + tpd (CLK-DATA2) from sampling ) at CLK rising (at CLKB falling)
13
MB40C338V
s CLAMP and AMP OPERATION
Amp/CLAMP circuit
- +
RVCLP
Clamp pulse
RVIN
Image signal
10 F
+
x 1.9 RADIN
-
R1
R2
Internal BIAS (0.6 x AVDD)
< For example, Sync on G signal input >
0.7 Vp-p
GVIN
PCLP
GVRT
1.33 VP-P (fixed) GADIN
GVCLP VRB
Contrast adjust : controlling the voltage difference between VRT and VRB (typ : VRT - VRB = 1.33 V) Brightness adjust : controlling the voltage difference between VCLP and VRB (typ : VCLP = VRB) 14
MB40C338V
s CLAMP SIGNAL and HOLD SIGNAL
HSYNC input
thHHOLD tsHHOLD thHHOLD tsHHOLD
HHOLD input
tWCLP
PCLP input
CLK output
s SERIAL DATA TRANSFER TIMING
DATA input
D10
D9
D8
D7
D1
D0
tWCKL tWCKH
tsDATA thDATA
CK input
tsCS thCS tWCSH
CS input
15
BVIN
75 10 F
PCLP
+3.3 V or +5 V (MB40C338V)
VCLP
Serial Data
31 BDB5 32 BDB4 33 BDB3 34 BDB2 35 BDB1 36 BDB0 (LSB) 37 DVSS 38 DVDD 39 BDA7 (MSB) 40 BDA6 41 BDA5 42 BDA4 43 BDA3 44 BDA2 45 BDA1 46 BDA0 (LSB) 47 AVDD 48 AVSS 49 DVSS 50 DVDD 51 GDB7 (MSB) 52 GDB6 53 GDB5 54 GDB4 55 GDB3 56 GDB2 57 GDB1 58 GDB0 (LSB) 59 DVDD 60 DVSS
1 RVIN 2 VRB 3 GVIN 4 GVM 5 BVIN 6 BVM 7 VREF 8 PCLP 9 AVDD 10 AVSS 11 RADIN 12 VRBM 13 GADIN 14 VESD 15 BADIN 16 RVRTM 17 GVRTM 18 BVRTM 19 RVCLP 20 GVCLP 21 BVCLP 22 AVSS 23 AVDD 24 CS 25 CK 26 DATA 27 DVSS 28 DVDD 29 BDB7 (MSB) 30 BDB6
PVSS 120 PVDD 119 HSNYC 118 HHOLD 117 PVDD 116 LPF 115 PVSS 114 RREF 113 RVRT 112 GVRT 111 BVRT 110 RVM 109 AVSS 108 AVDD 107 DVDD 106 DVSS 105 OF 104 DSYNC 103 DSYNCB 102 COUT 101 EXPCLK 100 EXPCLKB 99 EXCLK 98 ADCLKA 97 ADCLKB 96 CLK 95 CLKB 94 DVDD 93 DVSS 92 AVSS 91
16
0.001 F HHOLD
0.1 F 1.6 k
MB40C338V
PVDD (+3.3 V) PVSS (0 V) VRT
12 k
+
HSYNC
100 F
EXPCLK EXPCLKB EXCLK
RVIN
75
s TYPICAL APPLICATION
GVIN
10 F VRB
+
75
10 F
+
+
(LSB) RDA0 90 RDA1 89 RDA2 88 RDA3 87 RDA4 86 RDA5 85 RDA6 84 (MSB) RDA7 83 DVDD 82 DVSS 81 AVSS 80 AVDD 79 (LSB) RDB0 78 RDB1 77 RDB2 76 RDB3 75 RDB4 74 RDB5 73 RDB6 72 (MSB) RDB7 71 DVDD 70 DVSS 69 (LSB) GDA0 68 GDA1 67 GDA2 66 GDA3 65 GDA4 64 GDA5 63 GDA6 62 (MSB) GDA7 61 Note : Unexpresstion capacitance values are all 1 F DVSS (0 V) 100 F + DVDD (+3.3 V)
AVSS (0 V)
+
100 F
AVDD (+3.3 V)
MB40C338V
s USAGE PRECAUTIONS
Be sure to ground the pins of AVDD, DVDD, PVDD, VESD, RVRTM, GVRTM, BVRTM, VRBM, RVM, GVM, BVM and VREF via high-frequency capacitor. Place the high-frequency capacitor as close as possible to the pin.
s ORDERING INFORMATION
Part number MB40C338VPFV Package 120-pin plastic LQFP (FPT-120P-M21) Remark
17
MB40C338V
s PACKAGE DIMENSION
120-pin plastic LQFP (FPT-120P-M21)
18.000.20(.709.008)SQ 16.000.10(.630.004)SQ
90 61
91
60
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX "A"
0~8
120
31
LEAD No.
1
30
0.50(.020)
0.220.05 (.009.002)
0.08(.003)
M
0.145 .006
+0.05 -0.03 +.002 -.001
0.45/0.75 (.018/.030)
0.100.05 (.004.002) (Stand off) 0.25(.010)
C
1998 FUJITSU LIMITED F120033S-2C-2
Dimension in mm (inches)
18
MB40C338V
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0009 (c) FUJITSU LIMITED Printed in Japan

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